An embodiment of the VLIW processor of the kind set forth is disclosed in WO 00/33178.
A Very Long Instruction Word (VLIW) processor allows exploiting instruction-level parallelism in programs and thus executing more than one instruction at a time. A VLIW processor uses multiple, independent functional units to execute multiple operations in parallel. VLIW processors package multiple functional unit operations into one very long instruction.
Limitations of VLIW processing include limited hardware resources, limited parallelism and a large increase in code size. Limited hardware resources may be the functional units, the register file or the communication network. Anticipating these limitations by adding more resources has some serious drawbacks. For example, when increasing the number of functional units, the memory size and register file bandwidth will have to increase as well. Furthermore, a large number of read and write ports are necessary for accessing the register file, imposing a bandwidth that is difficult to support without a large cost in the size of the register file and degradation in clock speed.
For some applications to be run on the VLIW processor the limiting hardware resource may be the register file. A large register file could be used to prevent this. However, this has several drawbacks. First, a register file with many registers may create critical timing paths and therefore limit the cycle time of the processor. Second, as the number of directly addressable registers increases, the number of bits to specify the multiple registers within the instruction increases as well. Third, a register file with many registers occupies a large silicon area.